module pipeline_div_tb();
reg rst,clk,start;
    reg unsigned[7:0]diver,divee;
    wire unsigned[7:0]div,mod;
    wire unsigned[7:0]div_cmp,mod_cmp;
    always #5 clk=~clk;
	initial begin
	   $dumpfile("pipeline_div_tb.vcd");
	   $dumpvars();
	   #0 rst=1;clk=0;
	   #10 rst=0;
	   #60000 $finish;
	end
	assign div_cmp=divee/diver;
	assign mod_cmp=divee%diver;
	always@(posedge clk)
	begin
	  	
		  	diver<=$random+1;
			divee<=$random+1;
		  	if(div_cmp==div)
			  	$display("DIVIDE OKAY!\n");
			else 
				$display("DIVIDE FAIL!\n");
			if(mod_cmp==mod)
				$display("REMAIN OKAY!\n");
			else 
				$display("REMAIN FAIL!\n");
	end
    pipeline_div DUT
    (
      .clk(clk),
      .rst(rst),

      .dividend(divee),   //被除数
      .divisor(diver),    //除数

      .merchant (div),  //商位宽：N
      .remainder (mod)
      );


endmodule